Pallas Ethernet Adapter

In the past I designed a test board for transmission lines which had major flaws – not in the basic calculation of impedances but in the form and discontinuity of impedance at the transitions between pad and transmission line.

Determined to create a more practical example for high-speed data signals, I decided to put my energy into designing my own PCIe Ethernet Adapter with Microchip’s LAN7430 chip.

This chip is an all-in-one solution, its brother the LAN7431 is stripped down and missing the ethernet phy, by implementing the GMII or RGMII interface. With the well-publicized chip (evaluation circuit board with open schematic) it was a great starting point.

I began by creating a KiCAD project based on the PCIe template of Luca Anastasio, who had done an excellent job on the PCIe templates, with the design guidelines already baked into the board. All files and artifacts can be found in the Github project.

All files and artifacts can be found in the github project.
https://github.com/neuschs/Pallas-Ethernet-Adapter

Power delivery

Power delivery was a crucial aspect of the design and I chose to follow the same approach as the evaluation design of Microchip, tie the auxiliary power rail and the default 3V3 together with two Schottky diodes.

Every major different power rail is decoupled and filtered with capacitors and an inductor to suppress backwards switching noise.

To maintain the lowest impedance track path, I kept the supply pins of the LAN7430 as short as possible and the maximum width. Every supply section was connected to the according power supply in a star distribution pattern, and had a well-stitched ground reference plane below as a return path for the currents.

Ethernet

For educational purposes, I chose a dedicated magnetics module over an integrated MagJack module. This led to hours and days of searching for a fitting „tab down“ RJ45 connector because the LAN7430 has no pair swap mode to accommodate the swapped pairs on a „tab up variant.“

To avoid noise coupling into the ground plane from the galvanically isolated connector side, the ground fill beneath the transformer was restricted.

Keepout zones at the connector and the magnetics, as well as intra-pair skew adjustment via meandering, were also important considerations.

For better EMI performance, the PHY and the magnetics should be at least 25mm apart from each other, but I wasn’t able to fit them on the small board and wasn’t willing to change the whole layout for a first prototype.

For eventual usage of the IEEE 1588-2008 features, I added IPEX SMT connectors. With those, IPEX – SMA adapter cables, and some drilled holes in the PCIe bracket, it should be easy to make them available.

Impedance Control

On this PCB are two types of impedance-control relevant tracks. The PCIe lane and the Ethernet signals.

PCIe – Impedance

PCIe signals usually like to travel 100 Ohm differential and 50 Ohm single ended systems but (e.g. cables or the motherboard connection) but on the plugin card the PCI-SIG recommends 85 Ohm and 45 Ohm even though 100 Ohm would be less lossy.

Ethernet – Impedance

Assembly

All parts were sourced to be available at LCSC or directly in stock of JLCPCB to manufacture the PCBAs there – except the RJ45 connector due to the fact that it is THT. I will order a prototype at the beginning of February due to increased costs around Chinese New Year.

Overall, this was an exciting project that allowed me to delve deeper into the intricacies of high-speed data signals and Ethernet technology. With the detailed design guidelines and open-source schematic, it was a great learning experience and I look forward to testing the prototype and seeing how it performs in real-world scenarios.